Conventionally, a semiconductor device called a COF (chip on film) type has been used which includes a tape-shaped flexible wire substrate (tape carrier) and a semiconductor chip, such as an IC (integrated circuit) and an LSI (large-scale integrated circuit), bonded to and mounted on a surface thereof. For example, Japanese Laid-Open Patent Publication No. 176918/2001 (Tokukai 2001-176918; published on Jun. 29, 2001; corresponding to U.S. Pat. No. 6,518,649) discloses as one example of the COF-type semiconductor device a semiconductor device as shown in FIG. 10. FIG. 10 is a cross-sectional view of the COF-type semiconductor device.
In FIG. 10, the reference numeral 101 represents a semiconductor element, and the reference numeral 126 represents a tape carrier. Provided on a surface of the semiconductor element 101 is a gold bump 103, and the tape carrier 126 includes a tape base material 107, such as polyimide, and a wire pattern 104 of copper formed thereon. Further, provided partially on the tape base material 107 and the wire pattern 104 is a solder resist 110. The wire pattern 104 includes an inner lead 114 bonded to the gold bump 103 on the semiconductor element 101, an external connection terminal (outer lead) 113, a component pattern, and the like. The inner lead 114, which is an exposed part not coated with the solder resist 110, is provided with a tin plate 108, and the part-mounting pattern and the external connection terminal 113 are provided with a gold plate 106.
FIG. 11 is an enlarged cross-sectional view of a bonding part of the semiconductor element 101 and the tape carrier 126. As shown in FIG. 11, the gold bump 113 is formed on an electrode 102 of the semiconductor element 101. The tin plate 108 of the inner lead 114 and the gold bump 103 are bonded to each other with a eutectic alloy formed therebetween. Under such a condition that the gold bump 103 and the inner lead 114 are thus bonded to each other, the tape base material 107 covers an entire surface of the semiconductor element 101. Moreover, the bonding part of the semiconductor element 101 and the tape carrier 126 is sealed with a resin 111.
In manufacture of such a COF-type semiconductor device 125, the tape carrier 126 is longitudinal, and the semiconductor element 101 is mounted at regular intervals on the tape carrier 126 in the same direction with respect to a tape direction. In this mounting method, as shown in FIG. 11, the tin plate 108 provided on the wire pattern 104 of the tape base material 107 and the gold bump 103 provided on the electrode 102 of the semiconductor element 101 are heated from the back of the semiconductor element 101 (the surface reverse to the surface provided with the bump 103) and pressurized from the back of the wire pattern 104 of the tape base material 107. In this way, the eutectic alloy 109 of gold and tin is formed as described above, and the semiconductor element 101 is bonded to the tape carrier 126.
Mounting of the external connection terminal 113 is performed mainly by thermal pressure bonding with an ACF (anisotoropic conductive film) or by solder bonding.
Further, demands of users for a gold-plated connector are satisfied by two-color plating, i.e., by gold-plating only the external connection terminal 113 later. In a producing method of a two-color-plated tape carrier, a copper-plated tape carrier is etched to form a wire pattern, and after a solder resist is applied to the wire pattern, the wire pattern is subjected to a tin-plating treatment. That portion of the wire pattern 104 which is bonded to the semiconductor element 101 (inner lead 114) is coated with a wire-pattern protection mask, and the tin plate 108 on an exposed portion is removed. After removal of the tin plate 108, the portion is subjected to a gold-plating treatment. After the treatment, the wire-pattern protection mask is removed for inspection and shipment.
Meanwhile, conventionally, an element such as a chip capacitor has been mounted on a semiconductor package. The chip capacitor is mounted to remove a harmonic noise included in power supplied from the outside and prevent malfunction of a semiconductor element such as an LSI. A capacitor having such a function is called a bypass capacitor.
As one example of a semiconductor device provided with such a chip capacitor, Japanese Laid-Open Patent Publication No. 161923/1995 (Tokukaihei 7-161923; published on Jun. 23, 1995) discloses a semiconductor device as shown in FIG. 12. In this arrangement, there is a semiconductor package 201 with a chip 202 and a chip capacitor 204 mounted thereon. Provided on a central portion of the semiconductor package 201 is a cavity 208 for mounting the chip 102. Provided around the cavity 208 is a bonding stitch 207. Provided around the semiconductor package 201 is a drawing pad 210.
Such a semiconductor device is assembled as follows. First, the chip 102 is mounted in the cavity 208 with an Au—Si or silver paste, and an aluminum line is bonded to each terminal. Then, sealing is performed with a cap or the like for completion of the assembly. Thereafter, the chip capacitor 204 is bonded to the drawing pad 210 on the semiconductor package 201 with soldering or the like.
On one hand, as a market expands, there are a diversity of market demands for thin display devices such as liquid crystal display devices. On the other hand, in an ever-progressing field of thin display devices, development manufacturers are required to accelerate product development so as to lead the demands immediately to product commercialization, i.e., so as to shorten lead time. Similarly, in a filed of an integrated circuit device constituting a driving circuit section for driving a peripheral part and, in particular, a display panel, the development manufacturers are strongly required to shorten lead time.
In a field of liquid crystal display devices and, in particular, liquid crystal television sets among thin display devices, manufacturers are entering an era of fierce competition as an environment is created in which 40-or-more-inch liquid crystal television sets can be mass-produced. Particularly, a large-sized liquid crystal panel has a larger load capacitance, needs to be operated with a higher voltage and a higher frequency, and therefore is susceptible to noise and the like. Accordingly, as measures against such a problem, Japanese Laid-Open Patent Publication No. 161923/1995 describes an arrangement in which bypass capacitors and the like are mounted in a semiconductor device.
FIG. 13 shows one example of a wire in a conventional gate driver serving as a COF-type semiconductor device provided with the bypass capacitors for preventing malfunction of the semiconductor element. Note that, in FIG. 3, only power supply wires are shown and signal lines are not shown.
Right and left sides of an LSI chip 301 are supplied with a voltage (power supply voltage) VCC, a voltage (ground voltage) GND, a voltage (power supply voltage) VGH, and a voltage (power supply voltage) VGL. Here, a bypass capacitor is disposed between a supply line of the voltage GND and a supply line of the voltage VGL, between the supply line of the voltage GND and a supply line of the voltage VGH, between the supply line of the voltage GND and a supply line of the voltage VCC, and between a supply line of the VGH and a supply line of the VGL.
Specifically, a bypass capacitor c1 is provided between a wire 302 for supplying the voltage VGL and a wire 303 for supplying the voltage VGH. A bypass capacitor c2 is provided between the wire 303 for supplying the voltage VGH and a wire 304 for supplying the voltage GND. A bypass capacitor c3 is provided between the wire 304 for supplying the voltage GND and a wire 305 for supplying the voltage VCC.
Further, bypass capacitors c4 and c5 are provided between the other wire 306 for supplying the voltage VGL and the other wire 308 for supplying the voltage GND. Here, the bypass capacitor c5, inserted in parallel to the bypass capacitor c4, is used to increase a capacitance.
However, a conventional semiconductor device provided with a built-in bypass capacitor, requiring longer time for testing in a test step, more specifically, in a final test step, has such a problem that productivity decreases and cost increases.
That is, as shown in FIG. 13, although no bypass capacitor is connected to a wire 309 for supplying the voltage VCC and a wire 307 for supplying the voltage VGH, each of (i) the wires 302 and 306 for supplying the voltage VGL and (ii) the wires 304 and 308 for supplying the voltage GND is connected to a capacitor (the capacitor c1, c2, c3, or c4). Therefore, for such reasons as the capacitance of the bypass capacitors c1 to c4 connected to the wires 302, 306, 304, and 308, it takes a long time to supply the voltage VGL and the voltage GND to the LSI chip 301 for the purpose of testing. As a result, a test requires a long time.